1. Field of the Invention
The present invention relates to a method for constructing a multipurpose error-control code for multilevel memory cells operating with a variable number of storage levels, and to a multipurpose error-control method using said error-control code.
In particular, the present invention regards the definition of error-control codes for multilevel semiconductor memories and, more precisely, the definition of multipurpose linear block codes that enable error detection and correction in multilevel memories, maintaining the functionality thereof with memory cells operating with a different number of storage levels.
2. Description of the Related Art
As is known, thanks to the evolution of technological processes that make it possible to manufacture elementary devices of ever smaller dimensions, in the last few years semiconductor memories have been produced that have very high storage capacities.
A further increase in storage capacity has been achieved by resorting to multilevel storage, which makes it possible to increase the storage density, given the same technological generation. In fact, with this technique a number of information bits are stored within the individual memory cell normally used for storing a single bit.
It is moreover known that, in order to read a two-level memory cell (storing 1 bit), an appropriate electric quantity, linked to the state of the cell, is compared with a reference value, and, according to the outcome of the comparison, it may be determined whether the memory cell contains a logic “0” or a logic “1”.
In the case of cells that are able to store r bits, reading is carried out by comparing the electric quantity correlated to the state of the cell with 2r−1reference levels. The outcome of the comparisons enables determination in which of the 2r intervals allowed the cell is found, and consequently reconstruction of content of the cell in terms of binary information.
The multilevel approach can be applied both to volatile memories (such as DRAM memories) and to nonvolatile memories (such as EEPROM and Flash memories). In either case, the increase in the number of bits per cell renders more critical the tolerance to disturbance, the retention of the information and the accuracy of the operations of reading and writing. In addition, the increment of the storage capacity demanded by the market tends to reduce the overall reliability. For these reasons it is envisaged that the use of error control codes will be fundamental above all for high capacity multilevel memories.
At the moment, commercially available memory devices with larger capacities contain some hundreds of millions of bits, and in the next few years it is forecast that memory devices with ever-increasing capacities will become available.
The increase in the number of cells tends to reduce the mean time to failure (MTTF) of the entire memory device. However, given the need to create increasingly reliable equipment or systems, the level of reliability required for the individual memory component becomes increasingly stringent. For this reason, dedicated design techniques are adopted allied to careful quality control on the production processes in order to prevent or reduce failures.
However, malfunctioning of the memory chip cannot be eliminated completely and can be reduced only at the expense of a reduction in performance or an increase in costs.
A very effective way to increase reliability is represented by the design of memories immune from error using error-control codes, that is, codes that are able to detect and correct errors in the data stored in memories.
In particular, codes with correction of single error, or detection of double error and correction of single error, are used in semiconductor memory devices of various types. In this connection, see, for example, K. Furutani, K. Arimoto, H. Miyamoto, T. Kobayashi, K.-I. Yasuda, and K. Mashiko, “A Built-in Hamming Code ECC Circuit for DRAM's”, IEEE J. Solid-State Circuits, Vol. 24, No. 1, February 1989, pp. 50–56, and T. Tanzawa, T. Tanaka, K. Takeuchi, R. Shirota, S. Aritome, H. Watanabe, G. Hemink, K. Shimizu, S. Sato, Y. Takeuchi, K. Ohuchi, “A Compact On-Chip ECC For Low-Cost Flash Memories”, IEEE J. Solid-State Circuits, Vol. 32, No. 5, May 1997, pp. 662–669.
The errors in the memories are normally classified as “soft” errors and “hard” errors. By “soft” error is meant a random, non-repetitive and non-permanent change in the state of a cell. “Soft” errors are caused by occasional electrical noise or are induced by radiation (α particles, cosmic rays, etc.), regard a very limited number of cells at a time, and may be recovered in the next writing cycle.
By “hard” error is instead meant a permanent physical failure associated to faults present in the device or created during its operation owing to incapacity of the materials to withstand the stresses applied. Generally “hard” errors are much rarer than “soft” errors.
Error-control codes enable drastic reduction in the effects of “soft” errors, which represent the more serious problem of the two, especially for multilevel memories. They can moreover prove useful also for the purpose of recovering some “hard” errors.
To protect the information to be stored in the memory it is necessary to add, to the bits that form each information word, a certain number of control bits, appropriately calculated. The operation that associates to each information word a precise value of the control bits is called encoding. The control bits calculated by the circuit that carries out encoding must be stored together with the information word.
Each word stored will be subsequently read together with the control bits that pertain to it. The decoding circuit is able to detect and correct a certain number of erroneous bits per word by appropriately comparing the value of the control bits with the value of the information bits.
The number of control bits that it is necessary to add to each information word is determined according to the length of the information word itself and the number of errors per word that it is desired to correct.
More in general, error-control encoding can be extended from the binary alphabet (containing only the two symbols “0” and “1”) to a more extended alphabet containing q symbols. In this case, encoding consists in the addition of a certain number of symbols (no longer of bits) to each word to be stored, and the correction of the errors consists in the correction of the erroneous symbols.
This extension to the q-ary case is particularly suited to multilevel memories, in which each memory cell is able to store more than one bit (for example r bits). In this case, in fact, malfunctioning of one memory cell may degrade the value of all the bits stored in it. It is consequently more convenient to associate, to each block of r bits stored in a single cell, a q-ary symbol, i.e., one belonging to an alphabet constituted by q=2r different symbols. Each symbol is consequently stored in a different multilevel memory cell. In this way, each information word of k bits is viewed as a word formed by k/r q-ary symbols (equal to the number of memory cells that form each word), and the correction of a symbol is equivalent to the correction of all the r bits associated to it.
It is desirable that error-control methods integrated in a semiconductor memory satisfy three basic requisites:
the time required for the encoding operation and for the decoding operation (including error detection and correction) should affect the access time to the memory only to a minimum extent;
the additional area due to the encoding and decoding circuits and to the control cells should be minimized; and
the technique used should at least guarantee the correction of any type of error on the individual cell, which, in the case of multilevel cells, may consist of the error on a number of bits.
For the encoding and decoding times not to degrade the access time, the typical approach is to use parallel encoding structures or matrix structures, which offer the highest computation speeds. For a more detailed treatment of the subject, see, for example, C. V. Srinivasan, “Codes For Error Correction In High-Speed Memory Systems-Part I: Correction Of Cell Defects In Integrated Memories”, IEEE Trans. Comput., Vol. C-20, No. 8, August 1971, pp. 882–888.
As regards, instead, the second point, the area is minimized by choosing codes with characteristics suitable for the application and appropriately optimized.
The last point is finally guaranteed by the use of q-ary codes, which enable detection and correction of the errors on the memory cells, irrespective of the number of erroneous bits associated to each of them.
The multilevel memories designed to contain r bits per cell can, however, also operate by storing a smaller number of bits per cell. In this case, for writing and reading, it is possible to use a subset of the 2r−1 reference levels available. The extreme (and simplest) example of this operating condition is obtained when a multilevel memory is used as a normal two-level memory.
The choice of decreasing the number of levels reduces the storage capacity of the memory but increases its reliability. For example, in the case of nonvolatile memories, the reduction in the number of the levels enables guaranteeing the retention of the information for a longer time and in more unfavorable environmental conditions.
Normally, the choice of the operating modality is made in a permanent way by the manufacturer; in this case, the possibility referred to above may be interesting, for example, to obtain a memory with a smaller number of bits per cell as a subselection of one designed to contain a greater number of bits, in order to obtain an overall reduction in costs.
At present, however, to satisfy the growing demands of the market, memory devices are being designed in which also the end user can decide the operating modality on the basis of the type of use of the device, and there is consequently increasingly more felt the need to provide a multipurpose error-control method that is able, using the same circuits, to protect the data stored in cells that operate with a different number of levels.
This need is further strengthened by the fact that the memory devices of the coming generations, with large storage capacities, will be able to be configured sector by sector, and consequently will have internal sectors containing a different number of bits per cell (see, for example, U.S. Pat. No. 5,574,879).
Memory devices of this type will, for example, be able to be used in multimedia cards, enabling storage of the microcode for the microprocessor that manages the card in sectors with a low number of bits per cell, and storage of the user data in sectors with a high number of bits per cell.